C8051F850-C-GM Datasheet, PDF (229/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

22.10. Reset Sources Control Registers
Register 22.1. RSTSRC: Reset Source
Bit
7
6
Name Reserved FERROR
Type
R
R
Reset
0
X
SFR Address: 0xEF
5
C0RSEF
RW
X
4
SWRSF
RW
X
3
WDTRSF
R
X
2
MCDRSF
RW
X
1
PORSF
RW
X
0
PINRSF
R
X
Table 22.1. RSTSRC Register Bit Descriptions
Bit
Name
Function
7
Reserved Must write reset value.
6
FERROR Flash Error Reset Flag.
This read-only bit is set to 1 if a flash read/write/erase error caused the last reset.
5
C0RSEF Comparator0 Reset Enable and Flag.
Read: This bit reads 1 if Comparator0 caused the last reset.
Write: Writing a 1 to this bit enables Comparator0 (active-low) as a reset source.
4
SWRSF Software Reset Force and Flag.
Read: This bit reads 1 if last reset was caused by a write to SWRSF.
Write: Writing a 1 to this bit forces a system reset.
3
WDTRSF Watchdog Timer Reset Flag.
This read-only bit is set to 1 if a watchdog timer overflow caused the last reset.
2
MCDRSF Missing Clock Detector Enable and Flag.
Read: This bit reads 1 if a missing clock detector timeout caused the last reset.
Write: Writing a 1 to this bit enables the missing clock detector. The MCD triggers a reset
if a missing clock condition is detected.
1
PORSF Power-On / Supply Monitor Reset Flag, and Supply Monitor Reset Enable.
Read: This bit reads 1 anytime a power-on or supply monitor reset has occurred.
Write: Writing a 1 to this bit enables the supply monitor as a reset source.
0
PINRSF HW Pin Reset Flag.
This read-only bit is set to 1 if the RST pin caused the last reset.
Notes:
1. Reads and writes of the RSTSRC register access different logic in the device. Reading the register always returns
status information to indicate the source of the most recent reset. Writing to the register activates certain options as
reset sources. It is recommended to not use any kind of read-modify-write operation on this register.
2. When the PORSF bit reads back 1 all other RSTSRC flags are indeterminate.
3. Writing 1 to the PORSF bit when the supply monitor is not enabled and stabilized may cause a system reset.
Rev. 1.0
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