C8051F850-C-GM Datasheet, PDF (12/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

Table 1.3. Reset and Supply Monitor
Parameter
V_DD Supply Monitor Threshold
Power-On Reset (POR) Threshold
V_DD Ramp Time
Reset Delay from POR
Reset Delay from non-POR source
RST Low Time to Generate Reset
Missing Clock Detector Response
Time (final rising edge to reset)
Missing Clock Detector Trigger
Frequency
V_DD Supply Monitor Turn-On Time
Symbol
Test Condition
V_VDDM
V_POR
t_RMP
t_POR
t_RST
Rising Voltage on V_DD
Falling Voltage on V_DD
Time to V_DD > 2.2 V
Relative to V_DD >
V_POR
Time between release
of reset source and
code execution
t_RSTL
t_MCD
F_SYSCLK > 1 MHz
Min
1.85
—
0.75
10
3
—
15
—
F_MCD
—
t_MON
—
Typ
1.95
1.4
—
—
10
39
—
0.625
7.5
2
Max
2.1
—
1.36
—
31
—
—
1.2
13.5
—
Unit
V
V
V
µs
ms
µs
µs
ms
kHz
µs
Table 1.4. Flash Memory
Parameter
Symbol
Test Condition
Min Typ Max Units
Write Time^1,2
t_WRITE
One Byte,
19
20
21
µs
F_SYSCLK = 24.5 MHz
Erase Time^1,2
t_ERASE
One Page,
5.2
5.35
5.5
ms
F_SYSCLK = 24.5 MHz
V_DD Voltage During Programming³
V_PROG
2.2
—
3.6
V
Endurance (Write/Erase Cycles)
N_WE
20k 100k
— Cycles
Notes:
1. Does not include sequencing time before and after the write/erase operation, which may be multiple SYSCLK cycles.
2. The internal High-Frequency Oscillator has a programmable output frequency using the OSCICL register, which is
factory programmed to 24.5 MHz. If user firmware adjusts the oscillator speed, it must be between 22 and 25 MHz
during any flash write or erase operation. It is recommended to write the OSCICL register back to its reset value when
writing or erasing flash.
3. Flash can be safely programmed at any voltage above the supply monitor threshold (V_VDDM).
4. Data Retention Information is published in the Quarterly Quality and Reliability Report.
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Rev. 1.0