C8051F850-C-GM Datasheet, PDF (59/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

The upper 128 bytes of data memory are accessible only by indirect addressing. This region occupies the
same address space as the Special Function Registers (SFR) but is physically separate from the SFR
space. The addressing mode used by an instruction when accessing locations above 0x7F determines
whether the CPU accesses the upper 128 bytes of data memory space or the SFRs. Instructions that use
direct addressing will access the SFR space. Instructions using indirect addressing above 0x7F access the
upper 128 bytes of data memory. Figure 8.1 illustrates the data memory organization of the C8051F85x/
86x.
Revision C C8051F852/5 and C8051F862/5 devices implement the upper four bytes of internal RAM as a
32-bit Unique Identifier. More information can be found in “Device Identification and Unique Identifier” on
page 64.
8.2.1.1. General Purpose Registers
The lower 32 bytes of data memory, locations 0x00 through 0x1F, may be addressed as four banks of
general-purpose registers. Each bank consists of eight byte-wide registers designated R0 through R7.
Only one of these banks may be enabled at a time. Two bits in the program status word (PSW) register,
RS0 and RS1, select the active register bank. This allows fast context switching when entering subroutines
and interrupt service routines. Indirect addressing modes use registers R0 and R1 as index registers.
8.2.1.2. Bit Addressable Locations
In addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20
through 0x2F are also accessible as 128 individually addressable bits. Each bit has a bit address from
0x00 to 0x7F. Bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address
0x07. Bit 7 of the byte at 0x2F has bit address 0x7F. A bit access is distinguished from a full byte access by
the type of instruction used (bit source or destination operands as opposed to a byte source or
destination).
The MCS-51™ assembly language allows an alternate notation for bit addressing of the form XX.B where
XX is the byte address and B is the bit position within the byte. For example, the instruction:
MOV C, 22.3h
moves the Boolean value at 0x13 (bit 3 of the byte at location 0x22) into the Carry flag.
8.2.1.3. Stack
A programmer's stack can be located anywhere in the 256-byte data memory. The stack area is
designated using the Stack Pointer (SP) SFR. The SP will point to the last location used. The next value
pushed on the stack is placed at SP+1 and then SP is incremented. A reset initializes the stack pointer to
location 0x07. Therefore, the first value pushed on the stack is placed at location 0x08, which is also the
first register (R0) of register bank 1. Thus, if more than one register bank is to be used, the SP should be
initialized to a location in the data memory not being used for data storage. The stack depth can extend up
to 256 bytes.
8.2.2. External RAM
On devices with 512 bytes total RAM, there are 256 bytes of on-chip RAM mapped into the external data
memory space. All of these address locations may be accessed using the external move instruction
(MOVX) and the data pointer (DPTR), or using MOVX indirect addressing mode. Note: The 16-bit MOVX
instruction is also used for writes to the flash memory. See Section “10. Flash Memory” on page 57 for
details. The MOVX instruction accesses XRAM by default.
For a 16-bit MOVX operation (@DPTR), the upper 8 bits of the 16-bit external data memory address word
are "don't cares". As a result, addresses 0x0000 through 0x00FF are mapped modulo style over the entire
64 k external data memory address range. For example, the XRAM byte at address 0x0000 is shadowed
at addresses 0x0100, 0x0200, 0x0300, 0x0400, etc.
Revision C C8051F850/1/3/4 and C8051F860/1/3/4 devices implement the upper four bytes of external
RAM as a 32-bit Unique Identifier. More information can be found in “Device Identification and Unique
Identifier” on page 64.
Rev. 1.0
51