C8051F850-C-GM Datasheet, PDF (241/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

23.7. SPI Control Registers
Register 23.1. SPI0CFG: SPI0 Configuration
Bit
7
Name SPIBSY
Type
R
Reset
0
SFR Address: 0xA1
6
MSTEN
RW
0
5
CKPHA
RW
0
4
CKPOL
RW
0
3
SLVSEL
R
0
2
NSSIN
R
1
1
SRMT
R
1
0
RXBMT
R
1
Table 23.2. SPI0CFG Register Bit Descriptions
Bit
Name
Function
7
SPIBSY SPI Busy.
This bit is set to logic 1 when a SPI transfer is in progress (master or slave mode).
6
MSTEN Master Mode Enable.
0: Disable master mode. Operate in slave mode.
1: Enable master mode. Operate as a master.
5
CKPHA SPI0 Clock Phase.
0: Data centered on first edge of SCK period.
1: Data centered on second edge of SCK period.
4
CKPOL SPI0 Clock Polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
3
SLVSEL Slave Selected Flag.
This bit is set to logic 1 whenever the NSS pin is low indicating SPI0 is the selected
slave. It is cleared to logic 0 when NSS is high (slave not selected). This bit does not indi-
cate the instantaneous value at the NSS pin, but rather a de-glitched version of the pin
input.
2
NSSIN NSS Instantaneous Pin Input.
This bit mimics the instantaneous value that is present on the NSS port pin at the time
that the register is read. This input is not de-glitched.
1
SRMT Shift Register Empty (valid in slave mode only).
This bit will be set to logic 1 when all data has been transferred in/out of the shift register,
and there is no new information available to read from the transmit buffer or write to the
receive buffer. It returns to logic 0 when a data byte is transferred to the shift register
from the transmit buffer or by a transition on SCK. SRMT = 1 when in Master Mode.
Note: In slave mode, data on MOSI is sampled in the center of each data bit. In master mode, data on MISO is sampled one
SYSCLK before the end of each data bit, to provide maximum settling time for the slave device.
Rev. 1.0
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