C8051F850-C-GM Datasheet, PDF (139/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

16.7. Clock Selection Control Registers
Register 16.3. CLKSEL: Clock Select
Bit
7
6
5
4
Name Reserved
CLKDIV
Type
R
RW
Reset
0
0
1
1
SFR Address: 0xA9
3
2
Reserved
R
0
0
1
0
CLKSL
RW
0
0
Table 16.3. CLKSEL Register Bit Descriptions
Bit
Name
Function
7
Reserved Must write reset value.
6:4
CLKDIV Clock Source Divider.
This field controls the divider applied to the clock source selected by CLKSL. The output
of this divider is the system clock (SYSCLK).
000: SYSCLK is equal to selected clock source divided by 1.
001: SYSCLK is equal to selected clock source divided by 2.
010: SYSCLK is equal to selected clock source divided by 4.
011: SYSCLK is equal to selected clock source divided by 8.
100: SYSCLK is equal to selected clock source divided by 16.
101: SYSCLK is equal to selected clock source divided by 32.
110: SYSCLK is equal to selected clock source divided by 64.
111: SYSCLK is equal to selected clock source divided by 128.
3:2
Reserved Must write reset value.
1:0
CLKSL Clock Source Select.
Selects the system clock source.
00: Clock derived from the Internal High-Frequency Oscillator.
01: Clock derived from the External Oscillator circuit.
10: Clock derived from the Internal Low-Frequency Oscillator.
11: Reserved.
Rev. 1.0
122