C8051F850-C-GM Datasheet, PDF (175/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

Equation 20.4 describes the duty cycle when CEXnPOL in the PCA0POL regsiter is cleared to 0.
Equation 20.5 describes the duty cycle when CEXnPOL in the PCA0POL regsiter is set to 1. The
equations are true only when the lowest N bits of the PCA0CPn register are not all 0’s or all 1’s. With
CEXnPOL equal to zero, 100% duty cycle is produced when the lowest N bits of PCA0CPn are all 0, and
0% duty cycle is produced when the lowest N bits of PCA0CPn are all 1. For a given PCA resolution, the
unused high bits in the PCA0 counter and the PCA0CPn compare registers are ignored, and only the used
bits of the PCA0CPn register determine the duty cycle.
Note that although the PCA0CPn compare register determines the duty cycle, it is not always appropriate
for firmware to update this register directly. See the sections on 8 to 11-bit and 16-bit PWM mode for
additional details on adjusting duty cycle in the various modes.
Duty Cycle = ⁽---2---^N-----–----P---C----A-----0---C----P---n----⁾---–-----12---
2^N
Equation 20.4. N-bit Center-Aligned PWM Duty Cycle With CEXnPOL = 0 (N = PWM resolution)
PCA0CPn + ^1--
Duty Cycle
=
--------------------------------2--
2^N
Equation 20.5. N-bit Center-Aligned PWM Duty Cycle With CEXnPOL = 1 (N = PWM resolution)
Rev. 1.0
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