C8051F850-C-GM Datasheet, PDF (251/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

Table 24.1. SMBus Clock Source Selection
SMBCS
00
01
10
11
SMBus0 Clock Source
Timer 0 Overflow
Timer 1 Overflow
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
The SMBCS bit field selects the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 24.1.The selected
clock source may be shared by other peripherals so long as the timer is left running at all times.
T_HighMin
=
T_LowMin
=
----------------------1-----------------------
f_{ClockSourceOverflow}
Equation 24.1. Minimum SCL High and Low Times
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 24.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 24.2.
BitRate
=
-^f-^C----^l-^o---^c--^k--^S---^o--^u---^r--^c--^e--^O----^v--^e--^r--^f--^l-^o---^w-
3
Equation 24.2. Typical SMBus Bit Rate
Figure 24.4 shows the typical SCL generation described by Equation 24.2. Notice that T_HIGH is typically
twice as large as T_LOW. The actual SCL output may vary due to other devices on the bus (SCL may be
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 24.1.
Timer Source
Overflows
SCL
T_Low
T_High
SCL High Timeout
Figure 24.4. Typical SMBus SCL Generation
Rev. 1.0
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