C8051F850-C-GM Datasheet, PDF (250/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

For the SMBus0 interface, Timer 3 is used to implement SCL low timeouts. The SCL low timeout feature is
enabled by setting the SMB0TOE bit in SMB0CF. The associated timer is forced to reload when SCL is
high, and allowed to count when SCL is low. With the associated timer enabled and configured to overflow
after 25 ms (and SMB0TOE set), the timer interrupt service routine can be used to reset (disable and re-
enable) the SMBus in the event of an SCL low timeout.
24.3.5. SCL High (SMBus Free) Timeout
The SMBus specification stipulates that if the SCL and SDA lines remain high for more that 50 µs, the bus
is designated as free. When the SMB0FTE bit in SMB0CF is set, the bus will be considered free if SCL and
SDA remain high for more than 10 SMBus clock source periods (as defined by the timer configured for the
SMBus clock source). If the SMBus is waiting to generate a Master START, the START will be generated
following this timeout. A clock source is required for free timeout detection, even in a slave-only
implementation.
24.4. Using the SMBus
The SMBus can operate in both Master and Slave modes. The interface provides timing and shifting
control for serial transfers; higher level protocol is determined by user software. The SMBus interface
provides the following application-independent features:
Byte-wise serial data transfers
Clock signal generation on SCL (Master Mode only) and SDA data synchronization
Timeout/bus error recognition, as defined by the SMB0CF configuration register
START/STOP timing, detection, and generation
Bus arbitration
Interrupt generation
Status information
Optional hardware recognition of slave address and automatic acknowledgement of address/data
SMBus interrupts are generated for each data byte or slave address that is transferred. When hardware
acknowledgement is disabled, the point at which the interrupt is generated depends on whether the
hardware is acting as a data transmitter or receiver. When a transmitter (i.e., sending address/data,
receiving an ACK), this interrupt is generated after the ACK cycle so that software may read the received
ACK value; when receiving data (i.e., receiving address/data, sending an ACK), this interrupt is generated
before the ACK cycle so that software may define the outgoing ACK value. If hardware acknowledgement
is enabled, these interrupts are always generated after the ACK cycle. See Section 24.5 for more details
on transmission sequences.
Interrupts are also generated to indicate the beginning of a transfer when a master (START generated), or
the end of a transfer when a slave (STOP detected). Software should read the SMB0CN (SMBus Control
register) to find the cause of the SMBus interrupt. Table 24.5 provides a quick SMB0CN decoding
reference.
24.4.1. SMBus Configuration Register
The SMBus Configuration register (SMB0CF) is used to enable the SMBus Master and/or Slave modes,
select the SMBus clock source, and select the SMBus timing and timeout options. When the ENSMB bit is
set, the SMBus is enabled for all master and slave events. Slave events may be disabled by setting the
INH bit. With slave events inhibited, the SMBus interface will still monitor the SCL and SDA pins; however,
the interface will NACK all received addresses and will not generate any slave interrupts. When the INH bit
is set, all slave events will be inhibited following the next START (interrupts will continue for the duration of
the current transfer).
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