C8051F850-C-GM Datasheet, PDF (141/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

17. Comparators (CMP0 and CMP1)
C8051F85x/86x devices include two on-chip programmable voltage comparators, CMP0 and CMP1. The
two comparators are functionally identical, but have different connectivity within the device. A functional
block diagram is shown in Figure 17.1.
Port Pins (8)
Internal LDO
Positive Input
Selection
Port Pins (8)
GND
Negative Input
Selection
CMPn
Programmable
Hysteresis
CPn+
CPn-
CPnA
(asynchronous)
SYSCLK
DQ
Q
CPn
(synchronous)
Programmable
Response Time
Figure 17.1. Comparator Functional Block Diagram
17.1. System Connectivity
Comparator inputs are routed to port I/O pins or internal signals using the comparator mux registers. The
comparator’s synchronous and asynchronous outputs can optionally be routed to port I/O pins through the
port I/O crossbar. The output of either comparator may also be configured to generate a system interrupt.
CMP0 may also be used as a reset source, or as a trigger to kill a PCA output channel.
The CMP0 inputs are selected in the CPT0MX register, while CPT1MX selects the CMP1 inputs. The
CMXP field selects the comparator’s positive input (CPnP.x); the CMXN field selects the comparator’s neg-
ative input (CPnN.x). Table 17.1 through Table 17.4 detail the comparator input multiplexer options on the
C8051F85x/86x family. See the port I/O crossbar sections for details on configuring comparator outputs via
the digital crossbar. Comparator inputs can be externally driven from –0.25 V to (V_DD) + 0.25 V without
damage or upset.
Important Note About Comparator Inputs: The port pins selected as comparator inputs should be con-
figured as analog inputs in their associated port configuration register, and configured to be skipped by the
crossbar.
Rev. 1.0
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