C8051F850-C-GM Datasheet, PDF (28/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

2.1.3.1. Normal Mode
Normal mode encompasses the typical full-speed operation. The power consumption of the device in this
mode will vary depending on the system clock speed and any analog peripherals that are enabled.
2.1.3.2. Idle Mode
Setting the IDLE bit in PCON causes the hardware to halt the CPU and enter idle mode as soon as the
instruction that sets the bit completes execution. All internal registers and memory maintain their original
data. All analog and digital peripherals can remain active during idle mode.
Idle mode is terminated when an enabled interrupt is asserted or a reset occurs. The assertion of an
enabled interrupt will cause the IDLE bit to be cleared and the CPU to resume operation. The pending
interrupt will be serviced and the next instruction to be executed after the return from interrupt (RETI) will
be the instruction immediately following the one that set the Idle Mode Select bit. If Idle mode is terminated
by an internal or external reset, the CIP-51 performs a normal reset sequence and begins program
execution at address 0x0000.
2.1.3.3. Stop Mode (Regulator On)
Setting the STOP bit in PCON when STOPCF in REG0CN is clear causes the controller core to enter stop
mode as soon as the instruction that sets the bit completes execution. In stop mode the internal oscillator,
CPU, and all digital peripherals are stopped. Each analog peripheral may be shut down individually prior to
entering stop mode. Stop mode can only be terminated by an internal or external reset.
2.1.3.4. Shutdown Mode (Regulator Off)
Shutdown mode is an extension of the normal stop mode operation. Setting the STOP bit in PCON when
STOPCF in REG0CN is also set causes the controller core to enter shutdown mode as soon as the
instruction that sets the bit completes execution, and then the internal regulator is powered down. In
shutdown mode, all core functions, memories and peripherals are powered off. An external pin reset or
power-on reset is required to exit shutdown mode.
2.2. I/O
2.2.1. General Features
The C8051F85x/86x ports have the following features:
Push-pull or open-drain output modes and analog or digital modes.
Port Match allows the device to recognize a change on a port pin value and wake from idle mode
or generate an interrupt.
Internal pull-up resistors can be globally enabled or disabled.
Two external interrupts provide unique interrupt vectors for monitoring time-critical events.
Above-rail tolerance allows 5 V interface when device is powered.
2.2.2. Crossbar
The C8051F85x/86x devices have a digital peripheral crossbar with the following features:
Flexible peripheral assignment to port pins.
Pins can be individually skipped to move peripherals as needed for design or layout
considerations.
The crossbar has a fixed priority for each I/O function and assigns these functions to the port pins. When a
digital resource is selected, the least-significant unassigned port pin is assigned to that resource. If a port
pin is assigned, the crossbar skips that pin when assigning the next selected resource. Additionally, the
crossbar will skip port pins whose associated bits in the PnSKIP registers are set. This provides some
flexibility when designing a system: pins involved with sensitive analog measurements can be moved away
from digital I/O and peripherals can be moved around the chip as needed to ease layout constraints.
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