C8051F850-C-GM Datasheet, PDF (111/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

Register 14.5. ADC0PWR: ADC0 Power Control
Bit
7
6
5
4
3
2
1
0
Name
ADBIAS
ADMXLP ADLPM
ADPWR
Type
RW
RW
RW
RW
Reset
0
0
0
0
1
1
1
1
SFR Address: 0xDF
Table 14.8. ADC0PWR Register Bit Descriptions
Bit
Name
Function
7:6
ADBIAS Bias Power Select.
This field can be used to adjust the ADC's power consumption based on the conversion
speed. Higher bias currents allow for faster conversion times.
00: Select bias current mode 0. Recommended to use modes 1, 2, or 3.
01: Select bias current mode 1 (SARCLK <= 16 MHz).
10: Select bias current mode 2.
11: Select bias current mode 3 (SARCLK <= 4 MHz).
5
ADMXLP Mux and Reference Low Power Mode Enable.
Enables low power mode operation for the multiplexer and voltage reference buffers.
0: Low power mode disabled.
1: Low power mode enabled (SAR clock < 4 MHz).
4
ADLPM Low Power Mode Enable.
This bit can be used to reduce power to the ADC's internal common mode buffer. It can
be set to 1 to reduce power when tracking times in the application are longer (slower
sample rates).
0: Disable low power mode.
1: Enable low power mode (requires extended tracking time).
3:0
ADPWR Burst Mode Power Up Time.
This field sets the time delay allowed for the ADC to power up from a low power state.
When ADTM is set, an additional 4 SARCLKs are added to this time.
T_PWRTIME
=
8-----×_{-----A----D----P----W-----R---}
F_HFOSC
Rev. 1.0
97