C8051F850-C-GM Datasheet, PDF (180/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

20.6. PCA Control Registers
Register 20.1. PCA0CN: PCA Control
Bit
7
6
5
4
3
Name
CF
CR
Reserved
Type
RW
RW
R
Reset
0
0
0
0
0
SFR Address: 0xD8 (bit-addressable)
2
CCF2
RW
0
1
CCF1
RW
0
0
CCF0
RW
0
Table 20.3. PCA0CN Register Bit Descriptions
Bit
Name
Function
7
CF
PCA Counter/Timer Overflow Flag.
Set by hardware when the PCA Counter/Timer overflows from 0xFFFF to 0x0000. When
the Counter/Timer Overflow (CF) interrupt is enabled, setting this bit causes the CPU to
vector to the PCA interrupt service routine. This bit is not automatically cleared by hard-
ware and must be cleared by software.
6
CR
PCA Counter/Timer Run Control.
This bit enables/disables the PCA Counter/Timer.
0: PCA Counter/Timer disabled.
1: PCA Counter/Timer enabled.
5:3
Reserved Must write reset value.
2
CCF2 PCA Module 2 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF2 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine.
This bit is not automatically cleared by hardware and must be cleared by software.
1
CCF1 PCA Module 1 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF1 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine.
This bit is not automatically cleared by hardware and must be cleared by software.
0
CCF0 PCA Module 0 Capture/Compare Flag.
This bit is set by hardware when a match or capture occurs. When the CCF0 interrupt is
enabled, setting this bit causes the CPU to vector to the PCA interrupt service routine.
This bit is not automatically cleared by hardware and must be cleared by software.
160
Rev. 1.0