C8051F850-C-GM Datasheet, PDF (176/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

20.4.3. 8 to11-bit Pulse Width Modulator Modes
Each module can be used independently to generate a pulse width modulated (PWM) output on its
associated CEXn pin. The frequency of the output is dependent on the timebase for the PCA counter/timer,
and the setting of the PWM cycle length (8 through 11-bits). For backwards-compatibility with the 8-bit
PWM mode available on other devices, the 8-bit PWM mode operates slightly different than 9 through 11-
bit PWM modes. It is important to note that all channels configured for 8 to 11-bit PWM mode will use the
same cycle length. It is not possible to configure one channel for 8-bit PWM mode and another for 11-bit
mode (for example). However, other PCA channels can be configured to Pin Capture, High-Speed Output,
Software Timer, Frequency Output, or 16-bit PWM mode independently. Each channel configured for a
PWM mode can be individually selected to operate in edge-aligned or center-aligned mode.
20.4.3.1. 8-bit Pulse Width Modulator Mode
In 8-bit PWM mode, the duty cycle is determined by the value of the low byte of the PCA0CPn register
(PCA0CPLn). To adjust the duty cycle, PCA0CPLn should not normally be written directly. Instead, it is
recommended to adjust the duty cycle using the high byte of the PCA0CPn register (register PCA0CPHn).
This allows seamless updating of the PWM waveform, as PCA0CPLn is reloaded automatically with the
value stored in PCA0CPHn during the overflow edge (in edge-aligned mode) or the up edge (in center-
aligned mode).
Setting the ECOMn and PWMn bits in the PCA0CPMn register, and setting the CLSEL bits in register
PCA0PWM to 00b enables 8-Bit Pulse Width Modulator mode. If the MATn bit is set to 1, the CCFn flag for
the module will be set each time a match edge or up edge occurs. The COVF flag in PCA0PWM can be
used to detect the overflow (falling edge), which will occur every 256 PCA clock cycles.
20.4.3.2. 9 to 11-bit Pulse Width Modulator Mode
In 9 to 11-bit PWM mode, the duty cycle is determined by the value of the least significant N bits of the
PCA0CPn register, where N is the selected PWM resolution.
To adjust the duty cycle, PCA0CPn should not normally be written directly. Instead, it is recommended to
adjust the duty cycle by writing to an “Auto-Reload” register, which is dual-mapped into the PCA0CPHn
and PCA0CPLn register locations. The data written to define the duty cycle should be right-justified in the
registers. The auto-reload registers are accessed (read or written) when the bit ARSEL in PCA0PWM is
set to 1. The capture/compare registers are accessed when ARSEL is set to 0. This allows seamless
updating of the PWM waveform, as the PCA0CPn register is reloaded automatically with the value stored
in the auto-reload registers during the overflow edge (in edge-aligned mode) or the up edge (in center-
aligned mode).
Setting the ECOMn and PWMn bits in the PCA0CPMn register, and setting the CLSEL bits in register
PCA0PWM to 00b enables 8-Bit Pulse Width Modulator mode. If the MATn bit is set to 1, the CCFn flag for
the module will be set each time a match edge or up edge occurs. The COVF flag in PCA0PWM can be
used to detect the overflow or down edge.
The 9 to 11-bit PWM mode is selected by setting the ECOMn and PWMn bits in the PCA0CPMn register,
and setting the CLSEL bits in register PCA0PWM to the desired cycle length (other than 8-bits). If the
MATn bit is set to 1, the CCFn flag for the module will be set each time a match edge or up edge occurs.
The COVF flag in PCA0PWM can be used to detect the overflow or down edge.
Important Note About PCA0CPHn and PCA0CPLn Registers: When writing a 16-bit value to the
PCA0CPn registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn
bit to 0; writing to PCA0CPHn sets ECOMn to 1.
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