C8051F850-C-GM Datasheet, PDF (165/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

20. Programmable Counter Array (PCA0)
The Programmable Counter Array (PCA0) provides three channels of enhanced timer and PWM
functionality while requiring less CPU intervention than standard counter/timers. The PCA consists of a
dedicated 16-bit counter/timer and three 16-bit capture/compare modules. The counter/timer is driven by a
programmable timebase that can select between seven sources: system clock, system clock divided by
four, system clock divided by twelve, the external oscillator clock source divided by 8, low frequency
oscillator divided by 8, Timer 0 overflows, or an external clock signal on the ECI input pin. Each capture/
compare module may be configured to operate independently in one of six modes: Edge-Triggered
Capture, Software Timer, High-Speed Output, Frequency Output, 8 to 11-Bit PWM, or 16-Bit PWM.
Additionally, all PWM modes support both center and edge-aligned operation. The external oscillator and
LFO oscillator clock options allow the PCA to be clocked by an external oscillator or the LFO while the
internal oscillator drives the system clock. Each capture/compare module has its own associated I/O line
(CEXn) which is routed through the crossbar to port I/O when enabled. The I/O signals have
programmable polarity and Comparator 0 can optionally be used to perform a cycle-by-cycle kill operation
on the PCA outputs. A PCA block diagram is shown in Figure 20.1
SYSCLK
SYSCLK / 4
SYSCLK / 12
Timer 0 Overflow
EXTCLK / 8
L-F Oscillator / 8
ECI
Sync
Sync
Sync
SYSCLK
Comparator 0 Output
PCA0
PCA Counter
Channel 2
Mo_Cde_haC_no_nnt_ero_l l₁
CaptuMroe_Cd/e_hC_aCo_nom_nnpt_erao_lrle₀
CaptuMroed/eCCoomnptraorle
Capture / Compare
Control /
Configuration
Interrupt
Logic
Output
Drive
Logic
CEX2
CEX1
CEX0
Polarity Select
Comparator
Clear Enable
Figure 20.1. PCA0 Block Diagram
Rev. 1.0
145