C8051F850-C-GM Datasheet, PDF (252/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

Setting the EXTHOLD bit extends the minimum setup and hold times for the SDA line. The minimum SDA
setup time defines the absolute minimum time that SDA is stable before SCL transitions from low-to-high.
The minimum SDA hold time defines the absolute minimum time that the current SDA value remains stable
after SCL transitions from high-to-low. EXTHOLD should be set so that the minimum setup and hold times
meet the SMBus Specification requirements of 250 ns and 300 ns, respectively. Table 24.2 shows the
minimum setup and hold times for the two EXTHOLD settings. Setup and hold time extensions are
typically necessary for SMBus compliance when SYSCLK is above 10 MHz.
Table 24.2. Minimum SDA Setup and Hold Times
EXTHOLD
Minimum SDA Setup Time
Minimum SDA Hold Time
T_low – 4 system clocks
0
or
1 system clock + s/w delay^*
3 system clocks
1
11 system clocks
12 system clocks
Note: Setup Time for ACK bit transmissions and the MSB of all data transfers. When using software acknowledgment, the s/
w delay occurs between the time SMB0DAT or ACK is written and when SI0 is cleared. Note that if SI is cleared in the
same write that defines the outgoing ACK value, s/w delay is zero.
With the SMBTOE bit set, Timer 3 should be configured to overflow after 25 ms in order to detect SCL low
timeouts (see Section “24.3.4. SCL Low Timeout” on page 224). The SMBus interface will force the
associated timer to reload while SCL is high, and allow the timer to count when SCL is low. The timer
interrupt service routine should be used to reset SMBus communication by disabling and re-enabling the
SMBus.
SMBus Free Timeout detection can be enabled by setting the SMBFTE bit. When this bit is set, the bus will
be considered free if SDA and SCL remain high for more than 10 SMBus clock source periods (see
Figure 24.4).
24.4.2. SMBus Pin Swap
The SMBus peripheral is assigned to pins using the priority crossbar decoder. By default, the SMBus
signals are assigned to port pins starting with SDA on the lower-numbered pin, and SCL on the next
available pin. The SWAP bit in the SMBTC register can be set to 1 to reverse the order in which the SMBus
signals are assigned.
24.4.3. SMBus Timing Control
The SDD field in the SMBTC register is used to restrict the detection of a START condition under certain
circumstances. In some systems where there is significant mismatch between the impedance or the
capacitance on the SDA and SCL lines, it may be possible for SCL to fall after SDA during an address or
data transfer. Such an event can cause a false START detection on the bus. These kind of events are not
expected in a standard SMBus or I2C-compliant system. In most systems this parameter should not be
adjusted, and it is recommended that it be left at its default value.
By default, if the SCL falling edge is detected after the falling edge of SDA (i.e. one SYSCLK cycle or
more), the device will detect this as a START condition. The SDD field is used to increase the amount of
hold time that is required between SDA and SCL falling before a START is recognized. An additional 2, 4,
or 8 SYSCLKs can be added to prevent false START detection in systems where the bus conditions
warrant this.
227
Rev. 1.0