C8051F850-C-GM Datasheet, PDF (61/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

9. Special Function Register Memory Map
This section details the special function register memory map for the C8051F85x/86x devices.
Table 9.1. Special Function Register (SFR) Memory Map
F8 SPI0CN PCA0L
PCA0H PCA0CPL0 PCA0CPH0 P0MAT P0MASK VDM0CN
F0
B
P0MDIN P1MDIN
EIP1
-
-
PRTDRV PCA0PWM
E8 ADC0CN0 PCA0CPL1 PCA0CPH1 PCA0CPL2 PCA0CPH2 P1MAT P1MASK RSTSRC
E0 ACC
XBR0
XBR1
XBR2
IT01CF
-
EIE1
-
D8 PCA0CN PCA0MD PCA0CPM0 PCA0CPM1 PCA0CPM2 CRC0IN CRC0DAT ADC0PWR
D0 PSW
REF0CN CRC0AUTO CRC0CNT P0SKIP P1SKIP SMB0ADM SMB0ADR
C8 TMR2CN REG0CN TMR2RLL TMR2RLH TMR2L
TMR2H CRC0CN CRC0FLIP
C0 SMB0CN SMB0CF SMB0DAT ADC0GTL ADC0GTH ADC0LTL ADC0LTH OSCICL
B8
IP
ADC0TK
-
ADC0MX ADC0CF ADC0L
ADC0H
CPT1CN
B0
-
OSCLCN ADC0CN1 ADC0AC
-
DEVICEID REVID
FLKEY
A8
IE
CLKSEL CPT1MX CPT1MD SMB0TC DERIVID
-
-
A0
P2
SPI0CFG SPI0CKR SPI0DAT P0MDOUT P1MDOUT P2MDOUT
-
98 SCON0
SBUF0
-
CPT0CN PCA0CLR CPT0MD PCA0CENT CPT0MX
90
P1
TMR3CN TMR3RLL TMR3RLH TMR3L
TMR3H PCA0POL WDTCN
88 TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
PSCTL
80
P0
SP
DPL
DPH
-
-
-
PCON
0(8)
1(9)
2(A)
3(B)
4(C)
5(D)
6(E)
7(F)
(bit addressable)
Register
ACC
ADC0AC
ADC0CF
ADC0CN0
ADC0CN1
ADC0GTH
ADC0GTL
ADC0H
Table 9.2. Special Function Registers
Address Register Description
0xE0 Accumulator
0xB3 ADC0 Accumulator Configuration
0xBC ADC0 Configuration
0xE8 ADC0 Control 0
0xB2
0xC4
0xC3
0xBE
ADC0 Control 1
ADC0 Greater-Than High Byte
ADC0 Greater-Than Low Byte
ADC0 Data Word High Byte
Page
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Rev. 1.0
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