C8051F850-C-GM Datasheet, PDF (236/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

should be disabled (by clearing the SPIEN bit, SPI0CN.0) when changing the clock phase or polarity. The
clock and data line relationships for master mode are shown in Figure 23.5. For slave mode, the clock and
data relationships are shown in Figure 23.6 and Figure 23.7. Note that CKPHA should be set to 0 on both
the master and slave SPI when communicating between two Silicon Labs C8051 devices.
The SPI0 Clock Rate Register (SPI0CKR) controls the master mode serial clock frequency. This register is
ignored when operating in slave mode. When the SPI is configured as a master, the maximum data
transfer rate (bits/sec) is one-half the system clock frequency or 12.5 MHz, whichever is slower. When the
SPI is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the
system clock frequency, provided that the master issues SCK, NSS (in 4-wire slave mode), and the serial
input data synchronously with the slave’s system clock. If the master issues SCK, NSS, and the serial input
data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock
frequency. In the special case where the master only wants to transmit data to the slave and does not need
to receive data from the slave (i.e. half-duplex operation), the SPI slave can receive data at a maximum
data transfer rate (bits/sec) of 1/4 the system clock frequency. This is provided that the master issues SCK,
NSS, and the serial input data synchronously with the slave’s system clock.
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MISO/MOSI
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NSS (Must Remain High
in Multi-Master Mode)
Figure 23.5. Master Mode Data/Clock Timing
213
Rev. 1.0