C8051F850-C-GM Datasheet, PDF (315/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

27.5. Watchdog Timer Control Registers
Register 27.1. WDTCN: Watchdog Timer Control
Bit
7
Name
Type
Reset
0
SFR Address: 0x97
Bit
Name
7:0
WDTCN
6
5
4
3
2
1
0
WDTCN
RW
0
0
1
0
1
1
1
Table 27.1. WDTCN Register Bit Descriptions
Function
WDT Control.
The WDT control field has different behavior for reads and writes.
Read:
When reading the WDTCN register, the lower three bits (WDTCN[2:0]) indicate the cur-
rent timeout interval. Bit WDTCN.4 indicates whether the WDT is active (logic 1) or inac-
tive (logic 0).
Write:
Writing the WDTCN register can set the timeout interval, enable the WDT, disable the
WDT, reset the WDT, or lock the WDT to prevent disabling.
Writing to WDTCN with the MSB (WDTCN.7) cleared to 0 will set the timeout interval to
the value in bits WDTCN[2:0].
Writing 0xA5 both enables and reloads the WDT.
Writing 0xDE followed within 4 system clocks by 0xAD disables the WDT.
Writing 0xFF locks out the disable feature until the next device reset.
Rev. 1.0
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