C8051F850-C-GM Datasheet, PDF (280/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

25.2. Timer 2 and Timer 3
Timer 2 and Timer 3 are functionally equivalent, with the only differences being the top-level connections to
other parts of the system, as detailed in Table 25.1 and Table 25.2.
The timers are 16 bits wide, formed by two 8-bit SFRs: TMRnL (low byte) and TMRnH (high byte). Each
timer may operate in 16-bit auto-reload mode or (split) 8-bit auto-reload mode. The TnSPLIT bit in
TMRnCN defines the timer operation mode.
The timers may be clocked by the system clock, the system clock divided by 12, or the external oscillator
source divided by 8. Note that the external oscillator source divided by 8 is synchronized with the system
clock.
25.2.1. 16-bit Timer with Auto-Reload
When TnSPLIT is zero, the timer operates as a 16-bit timer with auto-reload. In this mode, the timer may
be configured to clock from SYSCLK, SYSCLK divided by 12, or the external oscillator clock source
divided by 8. As the 16-bit timer register increments and overflows from 0xFFFF to 0x0000, the 16-bit
value in the timer reload registers (TMRnRLH and TMRnRLL) is loaded into the main timer count register
as shown in Figure 25.4, and the High Byte Overflow Flag (TFnH) is set. If the timer interrupts are enabled,
an interrupt will be generated on each timer overflow. Additionally, if the timer interrupts are enabled and
the TFnLEN bit is set, an interrupt will be generated each time the lower 8 bits (TMRnL) overflow from
0xFF to 0x00.
TnXCLK
TnML
YSCLK / 12
0
TFnL
Overflow
0
TFnH
TCLK / 8
1
TRn
TCLK
TMRnL
TMRnH ^Overflow
Inter
SYSCLK
1
TFnLEN
TMRnRLL TMRnRLH
Reload
Figure 25.4. 16-Bit Mode Block Diagram
252
Rev. 1.0