C8051F850-C-GM Datasheet, PDF (103/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

The ADSJST bits can be used to format the contents of the 16-bit accumulator. The accumulated result
can be shifted right by 1, 2, or 3 bit positions. Based on the principles of oversampling and averaging, the
effective ADC resolution increases by 1 bit each time the oversampling rate is increased by a factor of 4.
The example below shows how to increase the effective ADC resolution by 1, 2, and 3 bits to obtain an
effective ADC resolution of 11-bit, 12-bit, or 13-bit respectively without CPU intervention.
Input Voltage
V_REF x 1023/1024
V_REF x 512/1024
V_REF x 511/1024
0
Repeat Count = 4
Shift Right = 1
11-Bit Result
0x07F7
0x0400
0x03FE
0x0000
Repeat Count = 16
Shift Right = 2
12-Bit Result
0x0FFC
0x0800
0x04FC
0x0000
Repeat Count = 64
Shift Right = 3
13-Bit Result
0x1FF8
0x1000
0x0FF8
0x0000
14.7. Programmable Window Detector
The ADC Programmable Window Detector continuously compares the ADC0 output registers to user-
programmed limits, and notifies the system when a desired condition is detected. This is especially
effective in an interrupt-driven system, saving code space and CPU bandwidth while delivering faster
system response times. The window detector interrupt flag (ADWINT in register ADC0CN0) can also be
used in polled mode. The ADC0 Greater-Than (ADC0GTH, ADC0GTL) and Less-Than (ADC0LTH,
ADC0LTL) registers hold the comparison values. The window detector flag can be programmed to indicate
when measured data is inside or outside of the user-programmed limits, depending on the contents of the
ADC0 Less-Than and ADC0 Greater-Than registers.
14.7.1. Window Detector In Single-Ended Mode
Figure 14.6 shows two example window comparisons for right-justified data, with
ADC0LTH:ADC0LTL = 0x0080 (128d) and ADC0GTH:ADC0GTL = 0x0040 (64d). The input voltage can
range from 0 to VREF x (1023/1024) with respect to GND, and is represented by a 10-bit unsigned integer
value. In the left example, an ADWINT interrupt will be generated if the ADC0 conversion word
(ADC0H:ADC0L) is within the range defined by ADC0GTH:ADC0GTL and ADC0LTH:ADC0LTL
(if 0x0040 < ADC0H:ADC0L < 0x0080). In the right example, and ADWINT interrupt will be generated if
the ADC0 conversion word is outside of the range defined by the ADC0GT and ADC0LT registers
(if ADC0H:ADC0L < 0x0040 or ADC0H:ADC0L > 0x0080). Figure 14.7 shows an example using left-
justified data with the same comparison values.
Rev. 1.0
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