C8051F850-C-GM Datasheet, PDF (178/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

20.5. Comparator Clear Function
In 8/9/10/11/16-bit PWM modes, the comparator clear function utilizes the Comparator0 output
synchronized to the system clock to clear CEXn to logic low for the current PWM cycle. This comparator
clear function can be enabled for each PWM channel by setting the CPCEn bits to 1 in the PCA0CLR SFR.
When the comparator clear function is disabled, CEXn is unaffected.
The asynchronous Comparator 0 output is logic high when the voltage of CP0+ is greater than CP0- and
logic low when the voltage of CP0+ is less than CP0-. The polarity of the Comparator 0 output is used to
clear CEXn as follows: when CPCPOL = 0, CEXn is cleared on the falling edge of the Comparator0 output
(see Figure 20.8); when CPCPOL = 1, CEXn is cleared on the rising edge of the Comparator0 output (see
Figure 20.9).
CEXn (CPCEn = 0)
Comparator0 Output
(CPCPOL = 0)
CEXn (CPCEn = 1)
Figure 20.8. CEXn with CPCEn = 1, CPCPOL = 0
CEXn (CPCEn = 0)
Comparator0 Output
(CPCPOL = 1)
CEXn (CPCEn = 1)
Figure 20.9. CEXn with CPCEn = 1, CPCPOL = 1
In the PWM cycle following the current cycle, should the Comparator 0 output remain logic low when
CPCPOL = 0 or logic high when CPCPOL = 1, CEXn will continue to be cleared. See Figure 20.10 and
Figure 20.11.
CEXn (CPCEn = 0)
Comparator0 Output
(CPCPOL = 0)
CEXn (CPCEn = 1)
Figure 20.10. CEXn with CPCEn = 1, CPCPOL = 0
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