C8051F850-C-GM Datasheet, PDF (174/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

20.4.2. Center Aligned PWM
When configured for center-aligned mode, a module will generate an edge transition at two points for every
2^(N+1) PCA clock cycles, where N is the selected PWM resolution in bits. In center-aligned mode, these
two edges are referred to as the “up” and “down” edges. The polarity at the output pin is selectable, and
can be inverted by setting the appropriate channel bit to ‘1’ in the PCA0POL register.
The generated waveforms are centered about the points where the lower N bits of the PCA0 counter are
zero. The (N+1)^th bit in the PCA0 counter acts as a selection between up and down edges. In 16-bit mode,
a special 17th bit is implemented internally for this purpose. At the center point, the (non-inverted) channel
output will be low when the (N+1)^th bit is ‘0’ and high when the (N+1)^th bit is ‘1’, except for cases of 0% and
100% duty cycle. Prior to inversion, an up edge sets the channel to logic high, and a down edge clears the
channel to logic low.
Down edges occur when the (N+1)^th bit in the PCA0 counter is one, and a logical inversion of the value in
the module’s PCA0CPn register matches the main PCA0 counter register for the lowest N bits. For
example, with 10-bit PWM, the down edge will occur when the one’s complement of bits 9-0 of the
PCA0CPn register match bits 9-0 of the PCA0 counter, and bit 10 of the PCA0 counter is ‘1’.
Up edges occur when the (N+1)^th bit in the PCA0 counter is zero, and the lowest N bits of the module’s
PCA0CPn register match the value of (PCA0 - 1). For example, with 10-bit PWM, the up edge will occur
when bits 9-0 of the PCA0CPn register are one less than bits 9-0 of the PCA0 counter, and bit 10 of the
PCA0 counter is ‘0’.
An example of the PWM timing in center-aligned mode for two channels is shown in Figure 20.7. In this
example, the CEX0POL and CEX1POL bits are cleared to 0.
PCA Clock
center
Counter (PCA0L) ^{0xFB 0xFC 0xFD 0xFE 0xFF 0x00 0x01 0x02 0x03 0x04}
Capture / Compare
(PCA0CPL0)
Output (CEX0)
0x01
center
down edge
up edge
Capture / Compare
(PCA0CPL1)
Output (CEX1)
0x04
center
down edge
Figure 20.7. Center-Aligned PWM Timing
up edge
154
Rev. 1.0