C8051F850-C-GM Datasheet, PDF (58/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

8.1. Program Memory
The CIP-51 core has a 64 kB program memory space. The C8051F85x/86x family implements 8 kB, 4 kB
or 2 kB of this program memory space as in-system, re-programmable flash memory. The last address in
the flash block (0x1FFF on 8 kB devices, 0x0FFF on 4 kB devices and 0x07FF on 2 kB devices) serves as
a security lock byte for the device, and provides read, write and erase protection. Addresses above the
lock byte within the 64 kB address space are reserved.
C8051F850/3
C8051F860/3
Lock Byte
Lock Byte Page
0x1FFF
0x1FFE
0x1E00
Flash Memory Space
C8051F851/4
C8051F861/4
Lock Byte
Lock Byte Page
0x0FFF
0x0FFE
0x0E00
Flash Memory Space
C8051F852/5
C8051F862/5
Lock Byte
Lock Byte Page
0x07FF
0x07FE
0x0600
0x0000
0x0000
Flash Memory Space
0x0000
Figure 8.2. Flash Program Memory Map
8.1.1. MOVX Instruction and Program Memory
The MOVX instruction in an 8051 device is typically used to access external data memory. On the
C8051F85x/86x devices, the MOVX instruction is normally used to read and write on-chip XRAM, but can
be re-configured to write and erase on-chip flash memory space. MOVC instructions are always used to
read flash memory, while MOVX write instructions are used to erase and write flash. This flash access
feature provides a mechanism for the C8051F85x/86x to update program code and use the program
memory space for non-volatile data storage. Refer to Section “10. Flash Memory” on page 57 for further
details.
8.2. Data Memory
The C8051F85x/86x device family includes up to 512 bytes of RAM data memory. 256 bytes of this
memory is mapped into the internal RAM space of the 8051. On devices with 512 bytes total RAM, 256
additional bytes of memory are available as on-chip “external” memory. The data memory map is shown in
Figure 8.1 for reference.
8.2.1. Internal RAM
There are 256 bytes of internal RAM mapped into the data memory space from 0x00 through 0xFF. The
lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. Either
direct or indirect addressing may be used to access the lower 128 bytes of data memory. Locations 0x00
through 0x1F are addressable as four banks of general purpose registers, each bank consisting of eight
byte-wide registers. The next 16 bytes, locations 0x20 through 0x2F, may either be addressed as bytes or
as 128 bit locations accessible with the direct addressing mode.
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