C8051F850-C-GM Datasheet, PDF (144/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

17.2. Functional Description
The comparator offers programmable response time and hysteresis, an analog input multiplexer, and two
outputs that are optionally available at the port pins: a synchronous “latched” output (CPn), or an
asynchronous “raw” output (CPnA). The asynchronous CPnA signal is available even when the system
clock is not active. This allows the comparator to operate and generate an output with the device in STOP
mode.
When disabled, the comparator output (if assigned to a port I/O pin via the crossbar) defaults to the logic
low state, and the power supply to the comparator is turned off.
The comparator response time may be configured in software via the CPTnMD register. Selecting a longer
response time reduces the comparator supply current.
Positive programmable
hysteresis (CPHYP)
CPn-
CPn+
CP0 (out)
Negative programmable
hysteresis (CPHYN)
Figure 17.2. Comparator Hysteresis Plot
The comparator hysteresis is software-programmable via its Comparator Control register CPTnCN. The
user can program both the amount of hysteresis voltage (referred to the input voltage) and the positive and
negative-going symmetry of this hysteresis around the threshold voltage.
The comparator hysteresis is programmable using the CPHYN and CPHYP fields in the Comparator
Control Register CPTnCN. The amount of negative hysteresis voltage is determined by the settings of the
CPHYN bits. As shown in Figure 17.2, settings of 20, 10, or 5 mV (nominal) of negative hysteresis can be
programmed, or negative hysteresis can be disabled. In a similar way, the amount of positive hysteresis is
determined by the setting the CPHYP bits.
Comparator interrupts can be generated on both rising-edge and falling-edge output transitions. The
CPFIF flag is set to logic 1 upon a comparator falling-edge occurrence, and the CPRIF flag is set to logic 1
upon the comparator rising-edge occurrence. Once set, these bits remain set until cleared by software.
The comparator rising-edge interrupt mask is enabled by setting CPRIE to a logic 1. The comparator
falling-edge interrupt mask is enabled by setting CPFIE to a logic 1.
The output state of the comparator can be obtained at any time by reading the CPOUT bit. The comparator
is enabled by setting the CPEN bit to logic 1, and is disabled by clearing this bit to logic 0.
Note that false rising edges and falling edges can be detected when the comparator is first powered on or
if changes are made to the hysteresis or response time control bits. Therefore, it is recommended that the
rising-edge and falling-edge flags be explicitly cleared to logic 0 a short time after the comparator is
enabled or its mode bits have been changed, before enabling comparator interrupts.
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