C8051F850-C-GM Datasheet, PDF (253/328 Pages) Silicon Laboratories – Low-Cost 8-bit MCU Family with up to 8 kB of Flash

24.4.4. SMB0CN Control Register
SMB0CN is used to control the interface and to provide status information. The higher four bits of SMB0CN
(MASTER, TXMODE, STA, and STO) form a status vector that can be used to jump to service routines.
MASTER indicates whether a device is the master or slave during the current transfer. TXMODE indicates
whether the device is transmitting or receiving data for the current byte.
STA and STO indicate that a START and/or STOP has been detected or generated since the last SMBus
interrupt. STA and STO are also used to generate START and STOP conditions when operating as a
master. Writing a 1 to STA will cause the SMBus interface to enter Master Mode and generate a START
when the bus becomes free (STA is not cleared by hardware after the START is generated). Writing a 1 to
STO while in Master Mode will cause the interface to generate a STOP and end the current transfer after
the next ACK cycle. If STO and STA are both set (while in Master Mode), a STOP followed by a START will
be generated.
The ARBLOST bit indicates that the interface has lost an arbitration. This may occur anytime the interface
is transmitting (master or slave). A lost arbitration while operating as a slave indicates a bus error
condition. ARBLOST is cleared by hardware each time SI is cleared.
The SI bit (SMBus Interrupt Flag) is set at the beginning and end of each transfer, after each byte frame, or
when an arbitration is lost; see Table 24.3 for more details.
Important Note About the SI Bit: The SMBus interface is stalled while SI is set; thus SCL is held low, and
the bus is stalled until software clears SI.
24.4.4.1. Software ACK Generation
When the EHACK bit in register SMB0ADM is cleared to 0, the firmware on the device must detect
incoming slave addresses and ACK or NACK the slave address and incoming data bytes. As a receiver,
writing the ACK bit defines the outgoing ACK value; as a transmitter, reading the ACK bit indicates the
value received during the last ACK cycle. ACKRQ is set each time a byte is received, indicating that an
outgoing ACK value is needed. When ACKRQ is set, software should write the desired outgoing value to
the ACK bit before clearing SI. A NACK will be generated if software does not write the ACK bit before
clearing SI. SDA will reflect the defined ACK value immediately following a write to the ACK bit; however
SCL will remain low until SI is cleared. If a received slave address is not acknowledged, further slave
events will be ignored until the next START is detected.
24.4.4.2. Hardware ACK Generation
When the EHACK bit in register SMB0ADM is set to 1, automatic slave address recognition and ACK
generation is enabled. More detail about automatic slave address recognition can be found in Section
24.4.5. As a receiver, the value currently specified by the ACK bit will be automatically sent on the bus
during the ACK cycle of an incoming data byte. As a transmitter, reading the ACK bit indicates the value
received on the last ACK cycle. The ACKRQ bit is not used when hardware ACK generation is enabled. If
a received slave address is NACKed by hardware, further slave events will be ignored until the next
START is detected, and no interrupt will be generated.
Table 24.3 lists all sources for hardware changes to the SMB0CN bits. Refer to Table 24.5 for SMBus
status decoding using the SMB0CN register.
Table 24.3. Sources for Hardware Changes to SMB0CN
Bit
MASTER
TXMODE
Set by Hardware When:
A START is generated.
START is generated.
SMB0DAT is written before the start of an
SMBus frame.
Cleared by Hardware When:
A STOP is generated.
Arbitration is lost.
A START is detected.
Arbitration is lost.
SMB0DAT is not written before the
start of an SMBus frame.
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