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SH7712 Datasheet, PDF (98/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series | |||
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Section 2 CPU
Table 2.6 Data Transfer Instructions
Instruction
Instruction Code Operation
Privileged
Mode
Cycles T Bit
MOV #imm,Rn
1110nnnniiiiiiii
Imm â Sign extension â Rn 
1

MOV.W @(disp,PC),Rn 1001nnnndddddddd
(disp x 2+PC)âSign extension 
â Rn
1

MOV.L @(disp,PC),Rn 1101nnnndddddddd (disp x 4+PC)âRn

1

MOV Rm,Rn
0110nnnnmmmm0011 RmâRn

1

MOV.B Rm,@Rn
0010nnnnmmmm0000 Rmâ(Rn)

1

MOV.W Rm,@Rn
0010nnnnmmmm0001 Rmâ(Rn)

1

MOV.L Rm,@Rn
0010nnnnmmmm0010 Rmâ(Rn)

1

MOV.B @Rm,Rn
0110nnnnmmmm0000 (Rm)âSign extensionâRn 
1

MOV.W @Rm,Rn
0110nnnnmmmm0001 (Rm)âSign extensionâRn 
1

MOV.L @Rm,Rn
0110nnnnmmmm0010 (Rm)âRn

1

MOV.B Rm,@âRn
0010nnnnmmmm0100 Rnâ1âRn, Rmâ(Rn)

1

MOV.W Rm,@âRn
0010nnnnmmmm0101 Rnâ2âRn, Rmâ(Rn)

1

MOV.L Rm,@âRn
0010nnnnmmmm0110 Rnâ4âRn, Rmâ(Rn)

1

MOV.B @Rm+,Rn
0110nnnnmmmm0100 (Rm)âSign extensionâRn, 
Rm+1âRm
1

MOV.W @Rm+,Rn
0110nnnnmmmm0101 (Rm)âSign extensionâRn,

Rm+2âRm
1

MOV.L @Rm+,Rn
0110nnnnmmmm0110 (Rm)âRn, Rm+4âRm

1

MOV.B R0,@(disp,Rn) 10000000nnnndddd R0â(disp+Rn)

1

MOV.W R0,@(disp,Rn) 10000001nnnndddd R0â(disp x 2+Rn)

1

MOV.L Rm,@(disp,Rn) 0001nnnnmmmmdddd Rmâ(disp x 4+Rn)

1

MOV.B @(disp,Rm),R0 10000100mmmmdddd (disp+Rm)âSign
extensionâR0

1

MOV.W @(disp,Rm),R0 10000101mmmmdddd (disp x 2+Rm)âSign
extensionâR0

1

MOV.L @(disp,Rm),Rn 0101nnnnmmmmdddd (disp x 4+Rm)âRn

1

MOV.B Rm,@(R0,Rn) 0000nnnnmmmm0100 Rmâ(R0+Rn)

1

MOV.W Rm,@(R0,Rn) 0000nnnnmmmm0101 Rmâ(R0+Rn)

1

MOV.L Rm,@(R0,Rn) 0000nnnnmmmm0110 Rmâ(R0+Rn)

1

Rev. 1.00 Dec. 27, 2005 Page 56 of 932
REJ09B0269-0100
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