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SH7712 Datasheet, PDF (102/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series | |||
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Section 2 CPU
Table 2.8 Logic Operation Instructions
Instruction
Instruction
Code
Operation
Privileged
Mode
Cycles T Bit
AND Rm,Rn
0010nnnnmmmm1001 Rn & Rm â Rn

1

AND #imm,R0
11001001iiiiiiii
R0 & imm â R0

1

AND.B
NOT
#imm,@(R0,
GBR)
Rm,Rn
11001101iiiiiiii
(R0+GBR) & imm â
(R0+GBR)
0110nnnnmmmm0111 â¼Rm â Rn

3


1

OR
Rm,Rn
0010nnnnmmmm1011 RnRm â Rn

1

OR
#imm,R0
11001011iiiiiiii
R0imm â R0

1

OR.B
#imm,@(R0, 11001111iiiiiiii
GBR)
(R0+GBR)imm â (R0+GBR) 
3

TAS.B @Rn
0100nnnn00011011 If (Rn) is 0, 1 â T; 1 â MSB of 
(Rn)
4
Test result
TST Rm,Rn
0010nnnnmmmm1000 Rn & Rm; if the result is 0, 1 â 
T
1
Test result
TST #imm,R0
11001000iiiiiiii
R0 & imm; if the result is 0, 1 
âT
1
Test result
TST.B #imm,@(R0, 11001100iiiiiiii
GBR)
(R0 + GBR) & imm; if the result 
is 0, 1 â T
3
Test result
XOR Rm,Rn
0010nnnnmmmm1010 Rn ^ Rm â Rn

1

XOR #imm,R0
11001010iiiiiiii
R0 ^ imm â R0

1

XOR.B #imm,@(R0, 11001110iiiiiiii
GBR)
(R0+GBR) ^ imm â (R0+GBR) 
3

Rev. 1.00 Dec. 27, 2005 Page 60 of 932
REJ09B0269-0100
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