SH7712 Datasheet, PDF (757/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
With EtherC, before storage of receive frames in the FIFO of E-DMAC/TSU is started, there is a
need to determine receive frame processing. The time limit for determining this processing is
within 52 clocks from RX_DV assertion.
Note: * Do not memorize MAC addresses overlapping with the internal CAM entry table of
this LSI during external CAM logic. If the CAMSEN0 or CAMSEN1 pin is asserted at
the same time as CAM hit occurs for the internal CAM entry table, evaluation may not
performed correctly.
Table 18.5 Receive Frame Process (When External CAM Logic is Used)
CAMSEN0 or
CAMSEN1 Pin
Frame
Normal Mode
MCT = 0
MCT = 1
Promiscuous Mode
MCT = 0
MCT = 1
Assertion
Frame to this LSI Discarded
Discarded
(when addresses
match)
Broadcast frame
Multicast frame
Discarded
Discarded
Received
Discarded
Discarded
Received
Frames to
destinations other
than this LSI
Received
Discarded
Negation
Frames to this LSI Received
Received
(when addresses do Broadcast frame
not match)
Multicast frame
Received
Received
Discarded
Received
Received
Discarded
Frames to
destinations other
than this LSI
Discarded
Received
[Legend]
MCT (Bit 13 in ECMR): Multicast receive mode (0: Received when CAM mishit/
1: Received when CAM hit)
Rev. 1.00 Dec. 27, 2005 Page 715 of 932
REJ09B0269-0100