SH7712 Datasheet, PDF (692/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 18 Ethernet Controller (EtherC)
18.3.5 PHY Interface Register (PIR)
PIR is a 32-bit readable/writable register that provides a means of accessing the PHY-LSI registers
via the MII.
Initial
Bit
Bit Name Value
R/W
31 to 4 
All 0
R
3
MDI
Undefined R
2
MDO
0
R/W
1
MMD
0
R/W
0
MDC
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
MII Management Data-In
Indicates the level of the MDIO pin.
MII Management Data-Out
Outputs the value set to this bit from the MDIO pin,
when the MMD bit is 1.
MII Management Mode
Specifies the data read/write direction with respect to
the MII.
0: Read direction is indicated
1: Write direction is indicated
MII Management Data Clock
Outputs the value set to this bit from the MDC pin
and supplies the MII with the management data
clock. For the method of accessing the MII registers,
see section 18.4.6, Accessing MII Registers.
Rev. 1.00 Dec. 27, 2005 Page 650 of 932
REJ09B0269-0100