SH7712 Datasheet, PDF (25/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 20 Pin Function Controller (PFC).........................................................779
20.1 Overview............................................................................................................................ 779
20.2 Register Configuration....................................................................................................... 780
20.3 Register Descriptions ......................................................................................................... 781
20.3.1 Port A Control Register (PACR) .......................................................................... 781
20.3.2 Port B Control Register (PBCR)........................................................................... 782
20.3.3 Port C Control Register (PCCR)........................................................................... 783
20.3.4 Ethernet Controller Pin Control Register (PETCR).............................................. 784
Section 21 I/O Ports ...........................................................................................787
21.1 Overview............................................................................................................................ 787
21.2 Register Descriptions ......................................................................................................... 787
21.2.1 Port A Data Register (PADR)............................................................................... 787
21.2.2 Port B Data Register (PBDR) ............................................................................... 788
21.2.3 Port C Data Register (PCDR) ............................................................................... 790
Section 22 User Debugging Interface (H-UDI) .................................................791
22.1 Features.............................................................................................................................. 791
22.2 Input/Output Pins ............................................................................................................... 792
22.3 Register Descriptions ......................................................................................................... 793
22.3.1 Bypass Register (SDBPR) .................................................................................... 793
22.3.2 Instruction Register (SDIR) .................................................................................. 793
22.3.3 Boundary Scan Register (SDBSR) ....................................................................... 794
22.3.4 ID Register (SDID)............................................................................................... 801
22.4 Operation ........................................................................................................................... 802
22.4.1 TAP Controller ..................................................................................................... 802
22.4.2 Reset Configuration .............................................................................................. 803
22.4.3 TDO Output Timing ............................................................................................. 803
22.4.4 H-UDI Reset ......................................................................................................... 804
22.4.5 H-UDI Interrupt .................................................................................................... 804
22.5 Boundary Scan ................................................................................................................... 805
22.5.1 Supported Instructions .......................................................................................... 805
22.5.2 Points for Attention............................................................................................... 806
22.6 Usage Notes ....................................................................................................................... 806
22.7 Advanced User Debugger (AUD)...................................................................................... 806
Section 23 List of Registers ...............................................................................807
23.1 Register Addresses (by functional module, in order of the corresponding
section numbers) ................................................................................................................ 808
23.2 Register Bits....................................................................................................................... 821
Rev. 1.00 Dec. 27, 2005 Page xxv of xlii