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SH7712 Datasheet, PDF (381/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series | |||
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Section 12 Bus State Controller (BSC)
Table 12.3 Address Space Map 2 (CMNCR.MAP = 1)
Physical Address
Area
Memory to be Connected
Capacity
Hâ²00000000 to Hâ²03FFFFFF Area 0
Normal memory*4
64 Mbytes
Burst ROM (Asynchronous)
Burst ROM (Synchronous)
Hâ²04000000 to Hâ²07FFFFFF Area 1
Internal I/O register area*3
64 Mbytes
Hâ²08000000 to Hâ²0BFFFFFF Area 2
Normal memory*4
64 Mbytes
Byte-selection SRAM
SDRAM
Hâ²0C000000 to Hâ²0FFFFFFF Area 3
Normal memory*4
64 Mbytes
Byte-selection SRAM
SDRAM
Hâ²10000000 to Hâ²13FFFFFF Area 4
Normal memory*4
64 Mbytes
Byte-selection SRAM
Burst ROM (Asynchronous)
Hâ²14000000 to Hâ²17FFFFFF Area 5*2 Normal memory*4
64 Mbytes
Byte-selection SRAM
PCMCIA
Hâ²18000000 to Hâ²1BFFFFFF Area 6*2 Normal memory*4
64 Mbytes
Byte-selection SRAM
PCMCIA
Hâ²1C000000 to Hâ²1FFFFFFF Area 7
Reserved area*1
64 Mbytes
Notes: 1. Do not access the reserved area. If the reserved area is accessed, the correct
operation cannot be guaranteed.
2. For area 5, CS5BBCR and CS5BWCR are valid.
For area 6, CS6BBCR and CS6BWCR are valid.
3. Set the top three bits of the address to 101 to allocate in the P2 space.
4. Memory that has an interface such as SRAM.
Rev. 1.00 Dec. 27, 2005 Page 339 of 932
REJ09B0269-0100
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