SH7712 Datasheet, PDF (946/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 Electrical Characteristics
SCIFnCK
TxD
(data trans-
mission)
RxD
(data
reception)
RTS
CTS
t_Scyc
t_TXD
t_RTSD
t_RXS t_RXH
t_CTSS t_CTSH
Figure 24.52 SCIF Input/Output Timing in Clock Synchronous Mode
24.3.10 SIOF Module Signal Timing
Table 24.12 SIOF Module Signal Timing
Item
(Conditions: V_CCQ = V_CCQ-RTC = 3.0 to 3.6 V, V_CC = V_CC-PLL1 = V_CC-PLL2 = 1.4 to 1.6 V,
V Q = V = V Q-RTC = V -PLL1 = V -PLL2 = 0 V, T = –20 to 75°C)
SS
SS
SS
SS
SS
a
Symbol Min.
Max. Unit Figure
SIOMCLK clock input cycle time
t_Mcyc
30
—
SIOMCLK input high-level width
t_MWH
0.4 × t_Mcyc
—
SIOMCLK input low-level width
t
MWL
0.4
×
t
Mcyc
—
SCK_SIO clock cycle time
t
SIcyc
2
×
t
Pcyc
—
SCK_SIO output high-level width t
SWHO
0.4
×
t
SIcyc
—
SCK_SIO output low-level width t
SWLO
0.4
×
t
SIcyc
—
SIOFSYNC output delay time
t
—
20
FSD
SCK_SIO input high-level width
t_SWHI
0.4 × t_SIcyc
—
SCK_SIO input low-level width
t_SWLI
0.4 × t_SIcyc
—
SIOFSYNC input setup time
t_FSS
20
—
SIOFSYNC input hold time
t_FSH
20
—
TXD_SIO output delay time
t
—
20
STDD
RXD_SIO input setup time
t
20
—
SRDS
RXD_SIO input hold time
t
20
—
SRDH
Note: t_Pcyc is the cycle time (ns) of the peripheral clock (Pφ).
ns 24.53
24.54 to 24.58
24.54 to 24.57
24.58
24.54 to 24.58
Rev. 1.00 Dec. 27, 2005 Page 904 of 932
REJ09B0269-0100