SH7712 Datasheet, PDF (640/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
17.3.6 SIOF Control Register (SICTR)
SICTR is used to set the SIOF operating state. SICTR is initialized by a power-on reset or
software reset.
Initial
Bit
Bit Name Value R/W
15
SCKE
0
R/W
14
FSE
0
R/W
13 to 10 —
All 0 R
9
TXE
0
R/W
Description
Serial Clock Output Enable
This bit is valid in master mode. If this bit is set to 1, the
SIOF initializes the baud rate generator and initiates the
operation. At the same time, the SIOF outputs the clock
generated in the baud rate generator to the SCK_SIO pin.
0: Disables the SCK_SIO output (outputs 0)
1: Enables the SCK_SIO output
Frame Synchronous Signal Output Enable
This bit is valid in master mode. If this bit is set to 1, the
SIOF initializes the frame counter and initiates the
operation.
0: Disables the SIOFSYNC output (outputs 0)
1: Enables the SIOFSYNC output
Reserved
These bits are always read as 0. The write value should
always be 0.
Transmission Enable
This bit setting becomes valid at the start of the next frame
(at the rising edge of the SIOFSYNC signal) and when
valid data is stored in the transmit FIFO. When the 1
setting for this bit becomes valid, the SIOF issues a
transmission transfer request according to the setting of
the TFWM bit in SIFCTR. When transmit data is stored in
the transmit FIFO, transmission of data from the TXD_SIO
pin begins. This bit is initialized by a transmit reset.
0: Disables data transmission from TXD_SIO (outputs 1)
1: Enables data transmission from TXD_SIO
Rev. 1.00 Dec. 27, 2005 Page 598 of 932
REJ09B0269-0100