SH7712 Datasheet, PDF (502/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Direct Memory Access Controller (DMAC)
Figure 13.1 shows a block diagram of the DMAC.
On-chip
memory
On-chip
peripheral module
DMA transfer request signal
DMA transfer acknowledge signal
Interrupt controller
DEIn
Iteration
control
Register
control
DMAC module
SAR_n
DAR_n
DMATCR_n
Start-up
control
Request
priority
control
CHCR_n
DMAOR
DMARS0-2
External ROM
External RAM
External I/O
(memory mapped)
External I/O
(with acknowledge-
ment)
DACK0, DACK1,
TEND0, TEND1
DREQ0, DREQ1
Bus
interface
Bus state
controller
Legend
SAR_n : DMA source address register
DAR_n : DMA destination address register
DMATCR_n: DMA transfer count register
CHCR_n : DMA channel control register
DMAOR : DMA operation register
DMARS0-2 : DMA extension resource selector
DEIn
: DMA transfer end interrupt request to the CPU
n
: 0, 1, 2, 3, 4, 5
Figure 13.1 Block Diagram of DMAC
Rev. 1.00 Dec. 27, 2005 Page 460 of 932
REJ09B0269-0100