SH7712 Datasheet, PDF (862/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 23 List of Registers
Abbreviation
Module*¹ Bus*²
Address
Access Size
Size (bit) (bit)*³
SDIR
H-UDI
P
H'A410 0200 16
16
SDID/SDIDH
P
H'A410 0214 32/16
32/16
SDIDL
P
H'A410 0216 16
16
Notes: 1. Module:
MMU:
Memory Management Unit
INTC:
Interrupt Controller
UBC:
User Break Controller
CPG:
Clock Pulse Generator
BSC:
Bus State Controller
DMAC:
Direct Memory Access Controller
TMU:
Timer Unit
RTC:
Realtime Clock
SCIF0:
Serial Communication Interface with FIFO 0
SCIF1:
Serial Communication Interface with FIFO 1
SIOF0:
Serial I/O with FIFO 0
SIOF1:
Serial I/O with FIFO 1
EtherC (MAC-0): Ethernet Controller 0
EtherC (MAC-1): Ethernet Controller 1
EtherC (TSU): Transfer Unit for Ethernet Controller
E-DMAC0:
Ethernet Controller Direct Memory Access Controller 0
E-DMAC1:
Ethernet Controller Direct Memory Access Controller 1
PFC:
Pin Function Controller
H-UDI:
User Debugging Interface
2. Bus:
L: Connected to the CPU, DSP, CCN, Cache, MMU, and UBC.
I: Connected to the BSC, CCN, Cache, DMAC, E-DMAC0, and E-DMAC1.
P: Connected to the BSC and peripheral modules (RTC, TMU, SCIF0, SCIF1,
SIOF0, SIOF1, DMAC, PORT, INTC, H-UDI, CPG).
3. The access size indicates the size when accessing (read/write) the control registers. If
an access is performed in the different size as shown above, the result is not correct
data.
4. 16 bits when writing and 8 bits when reading.
Rev. 1.00 Dec. 27, 2005 Page 820 of 932
REJ09B0269-0100