SH7712 Datasheet, PDF (487/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 12 Bus State Controller (BSC)
Th
T1
Tw
T2
Th
CKIO
A25 to A0
CSn
WEn(BEn)
RD/WR
Read
RD
D31 to D0
RD/WR
Write
RD
D31 to D0
BS
High
DACKn*
Note: The waveform for DACKn is when active low is specified.
Figure 12.35 Wait Timing for Byte-Selection SRAM (BAS = 1) (Software Wait Only)
Rev. 1.00 Dec. 27, 2005 Page 445 of 932
REJ09B0269-0100