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SH7712 Datasheet, PDF (101/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series | |||
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Section 2 CPU
Instruction
Instruction Code Operation
Privileged
Mode
Cycles T Bit
DT
Rn
0100nnnn00010000 Rn â 1 â Rn, if Rn = 0, 1 â T, 
else 0 â T
1
Comparison
result
EXTS.B
Rm,Rn
0110nnnnmmmm1110 A byte in Rm is sign-extended 
â Rn
1

EXTS.W Rm,Rn
0110nnnnmmmm1111 A word in Rm is sign-extended 
â Rn
1

EXTU.B
Rm,Rn
0110nnnnmmmm1100 A byte in Rm is zero-extended 
â Rn
1

EXTU.W Rm,Rn
0110nnnnmmmm1101 A word in Rm is zero-extended 
â Rn
1

MAC.L
@Rm+, 0000nnnnmmmm1111 Signed operation of (Rn) Ã

@Rn+
(Rm) + MAC â MAC,Rn + 4
â Rn, Rm + 4 â Rm,
32 Ã 32 + 64 â 64 bits
2 (to 5)* 
MAC.W
@Rm+, 0100nnnnmmmm1111 Signed operation of (Rn) Ã

@Rn+
(Rm) + MAC â MAC,Rn + 2
â Rn, Rm + 2 â Rm,
16 Ã 16 + 64 â 64 bits
2 (to 5)* 
MUL.L
Rm,Rn
0000nnnnmmmm0111 Rn à Rm â MACL,
32 Ã 32 â 32 bits

2 (to 5)* 
MULS.W Rm,Rn
0010nnnnmmmm1111 Signed operation of Rn à Rm 
â MACL,
16 Ã 16 â 32 bits
1( to 3)* 
MULU.W Rm,Rn 0010nnnnmmmm1110 Unsigned operation of

1(to 3)* 
Rn à Rm â MACL,
16 Ã 16 â 32 bits
NEG
Rm,Rn 0110nnnnmmmm1011 0âRmâRn

1

NEGC
Rm,Rn 0110nnnnmmmm1010 0âRmâTâRn, BorrowâT

1
Borrow
SUB
Rm,Rn 0011nnnnmmmm1000 RnâRmâRn

1

SUBC
Rm,Rn 0011nnnnmmmm1010 RnâRmâTâRn, Borrow âT 
1
Borrow
SUBV
Rm,Rn 0011nnnnmmmm1011 RnâRmâRn, UnderflowâT 
1
Underflow
Note: * The number of execution cycles indicated within the parentheses ( ) are required when
the operation result is read from the MACH/MACL register immediately after the
instruction.
Rev. 1.00 Dec. 27, 2005 Page 59 of 932
REJ09B0269-0100
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