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| SH7712 Datasheet, PDF (182/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series | |||
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Section 3 DSP Operating Unit
3.6 DSP Extended Function Instruction Set
3.6.1 CPU Extended Instructions
Table 3.35 DSP Mode Extended System Control Instructions
Instruction
Instruction Code Operation
SETRC #imm
10000010iiiiiiii
immâRC (of SR)
SETRC Rn
0100nnnn00010100 Rn[11:0] âRC(of SR)
LDRS @(disp,PC) 10001100dddddddd (disp x 2 + PC) âRS
LDRE @(disp,PC) 10001110dddddddd (disp x 2 + PC) âRE
STC MOD,Rn
0000nnnn01010010 MODâRn
STC RS,Rn
0000nnnn01100010 RSâRn
STC RE,Rn
0000nnnn01110010 REâRn
STS DSR,Rn
0000nnnn01101010 DSRâRn
STS A0,Rn
0000nnnn01111010 A0âRn
STS X0,Rn
0000nnnn10001010 X0âRn
STS X1,Rn
0000nnnn10011010 X1âRn
STS Y0,Rn
0000nnnn10101010 Y0âRn
STS Y1,Rn
0000nnnn10111010 Y1âRn
STS.L DSR,@-Rn 0100nnnn01100010 Rn-4âRn, DSRâ(Rn)
STS.L A0,@-Rn 0100nnnn01110010 Rn-4âRn, A0â(Rn)
STS.L X0,@-Rn 0100nnnn10000010 Rn-4âRn, X0â(Rn)
STS.L X1,@-Rn 0100nnnn10010010 Rn-4âRn, X1â(Rn)
STS.L Y0,@-Rn 0100nnnn10100010 Rn-4âRn, Y0â(Rn)
STS.L Y1,@-Rn 0100nnnn10110010 Rn-4âRn, Y1â(Rn)
STC.L MOD,@-Rn 0100nnnn01010011 Rn-4âRn, MODâ(Rn)
STC.L RS,@-Rn 0100nnnn01100011 Rn-4âRn, RSâ(Rn)
STC.L RE,@-Rn 0100nnnn01110011 Rn-4âRn, REâ(Rn)
LDS.L @Rn + ,DSR 0100nnnn01100110 (Rn) âDSR, Rn + 4âRn
LDS.L @Rn + ,A0 0100nnnn01110110 (Rn) âA0, Rn + 4âRn
LDS.L @Rn + ,X0 0100nnnn10000110 (Rn) âX0, Rn + 4âRn
LDS.L @Rn + ,X1 0100nnnn10010110 (Rn) âX1, Rn + 4âRn
Execution
States
T Bit Category
1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Rev. 1.00 Dec. 27, 2005 Page 140 of 1044
REJ09B0269-0100
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