SH7712 Datasheet, PDF (907/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 Electrical Characteristics
24.3.2 Control Signal Timing
Table 24.6 Control Signal Timing
(Conditions: V Q = V Q-RTC = 3.0 to 3.6 V, V = V -PLL1 = V -PLL2 = 1.4 to 1.6 V,
CC
CC
CC
CC
CC
V_SSQ = V_SS = V_SSQ-RTC = V_SS-PLL1 = V_SS-PLL2 = 0 V, T_a = –20 to 75°C)
66.67 MHz*²
Item
Symbol
Min.
Max.
Unit Figure
RESETP pulse width
RESETP setup time*¹
RESETM pulse width
RESETM setup time
BREQ setup time
BREQ hold time
NMI setup time*¹
t
RESPW
t
RESPS
t
RESMW
t_RESMS
t_BREQS
t_BREQH
t_NMIS
20*³
—
20
—
20*⁴
—
10
—
1/2 t_cyc+10 —
1/2 t_cyc+3 —
10
—
t
24.12
cyc
ns
t
cyc
ns
24.14
24.13
NMI hold time
IRQ5 to IRQ0 setup time*¹
t
NMIH
t
IRQS
3
—
10
—
IRQ5 to IRQ0 hold time
BACK delay time
t
IRQH
t
BACKD
3
—
—
1/2 t +13
cyc
24.14
STATUS1, STATUS0 delay time
t
STD
—
18
IRQOUT delay time
t_IRQOTD
—
1/2 t_cyc+12
24.15
24.16
Bus tri-state delay time 1
t_BOFF1
0
30
24.14,
Bus tri-state delay time 2
t_BOFF2
0
30
24.15
Bus buffer-on time 1
t_BON1
0
30
Bus buffer-on time 2
t
BON2
0
30
Notes: t is the external bus clock cycle (B clock cycle).
cyc
1. RESETP, NMI, and IRQ5 to IRQ0 are asynchronous. Changes are detected at the
clock rise when the setup shown is kept. When the setup cannot be kept, detection can
be delayed until the next clock rises.
2. The upper limit of the external bus clock is 66.67 MHz.
3. In standby mode, t = t (10 ms). When the crystal oscillation continues or the
RESPW
OSC2
clock multiplication ratio is changed in standby mode, t = t (100 µs).
RESPW
PLL1
4. In standby mode, t_RESMW = t_OSC2 (10 ms). When the crystal oscillation continues or the
clock multiplication ratio is changed in standby mode, RESETM must be kept low until
STATUS (0-1) changes to reset (HH).
Rev. 1.00 Dec. 27, 2005 Page 865 of 932
REJ09B0269-0100