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SH7712 Datasheet, PDF (212/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series | |||
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Section 4 Exception Handling
⢠Save address
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
⢠Exception code
An exception occurred during read: Hâ²040
An exception occurred during write: Hâ²060
⢠Remarks
The logical address (32 bits) that caused the exception is set in TEA and the MMU registers
are updated. The vector address of the TLB miss exception becomes VBR + H'0400. To speed
up TLB miss processing, the offset differs from other exceptions.
TLB invalid exception:
⢠Conditions
Comparison of TLB addresses shows address match but V = 0.
⢠Types
Instruction synchronous, re-execution type
⢠Save address
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
⢠Exception code
An exception occurred during read: Hâ²040
An exception occurred during write: Hâ²060
⢠Remarks
The logical address (32 bits) that caused the exception is set in TEA and the MMU registers
are updated.
TLB protection exception:
⢠Conditions
When a hit access violates the TLB protection information (PR bits).
⢠Types
Instruction synchronous, re-execution type
Rev. 1.00 Dec. 27, 2005 Page 170 of 932
REJ09B0269-0100
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