SH7712 Datasheet, PDF (830/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 I/O Ports
Table 21.1 Port A Data Register (PADR) Read/Write Operations
PAnMD1 PAnMD0 Pin State
Read
Write
0
0
Other function PADR value Value is written to PADR, but does not
affect pin state.
1
Output
PADR value Write value is output from pin.
1
0
Input (Pull-up Pin state
Value is written to PADR, but does not
MOS on)
affect pin state.
1
Input (Pull-up Pin state
Value is written to PADR, but does not
MOS off)
affect pin state.
[Legend]
n = 0 to 7
21.2.2 Port B Data Register (PBDR)
PBDR is an 8-bit readable/writable register that stores the data for pins PTB7 to PTB0. Bits
PB7DT to PB0DT correspond to the pins PTB7 to PTB0. PBDR is initialized to H′00 by a power-
on reset but is not initialized by a manual reset, in standby mode, or sleep mode.
Initial
Bit Bit Name Value
7
PB7DT
0
6
PB6DT
0
5
PB5DT
0
4
PB4DT
0
3
PB3DT
0
2
PB2DT
0
1
PB1DT
0
0
PB0DT
0
R/W Description
R/W
When the pin function is general output port, if the port
R/W
is read, the value of the corresponding PBDR bit is
returned directly. When the function is general input
R/W
port, if the port is read, the corresponding pin level is
R/W
read. Tables 21.2 and 21.3 show the function of
PBDR.
R/W
R/W
R/W
R/W
Rev. 1.00 Dec. 27, 2005 Page 788 of 932
REJ09B0269-0100