SH7712 Datasheet, PDF (930/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 24 Electrical Characteristics
CKIO
A25 to A0
A12/A11*1
Tp
Tpw
Tr
Tc1
Tc2
Tc3
Tc4
t_AD1
t_AD1
t_AD1
t_AD1
t_AD1
t_AD1
Row address
Column
address
(1-4)
t_AD1
t_AD1
t_AD1
t_AD1
Write command
CSn
RD/WR
RAS
CAS
DQMxx
D31 to D0
BS
t_CSD1
t_RWD1
t_RWD1
t_RWD1
t_RASD1
t_RASD1
t_RASD1
t_RASD1
t_CASD1
t_DQMD1
t_WDD2
t_WDH2
t_BSD
t_CSD1
t_RWD1
t_RASD1
t_CASD1
t_DQMD1
t_WDD2
t_WDH2
t_BSD
CKE
DACKn*²
t_DACD
(High)
t_DACD
Notes: 1. Address pin to be connected to A10 of SDRAM.
2. DACKn is a waveform when active-low is specified.
Figure 24.35 Synchronous DRAM Burst Write Bus Cycle (Single Write × 4)
(Bank Active Mode, PRE + ACTV + WRITE Commands,
Different Row Address, TRCD = 1 Cycle, TRWL = 1 Cycle)
Rev. 1.00 Dec. 27, 2005 Page 888 of 932
REJ09B0269-0100