SH7712 Datasheet, PDF (513/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 13 Direct Memory Access Controller (DMAC)
13.3.6 DMA Extension Resource Selector 0 to 2 (DMARS0 to DMARS2)
DMARS is a 16-bit readable/writable register that specifies the DMA transfer sources from
peripheral modules in each channel. DMARS0 specifies for channels 0 and 1, DMARS1 specifies
for channels 2 and 3, and DMARS2 specifies for channels 4 and 5. This register can set the
transfer requests of the SCIF0, SCIF1, SIOF0, and SIOF1.
When MID and RID other than the values listed in table 13.2 are set, the operation of this LSI is
not guaranteed. The transfer request from DMARS is valid only when bits RS3 to RS0 has been
set to B'1000 in CHCR0 to CHCR5. Otherwise, even if DMARS has been set, a transfer request
source is not accepted.
DMARS is initialized to H'0000 at reset and retains the current value in standby or module
standby mode.
• DMARS0
Initial
Bit
Bit Name Value R/W Description
15
C1MID5 0
R/W Transfer request module ID for DMA channel 1 (MID)
14
C1MID4 0
R/W See table 13.2.
13
C1MID3 0
R/W
12
C1MID2 0
R/W
11
C1MID1 0
R/W
10
C1MID0 0
R/W
9
C1RID1 0
R/W Transfer request register ID for DMA channel 1 (RID)
8
C1RID0 0
R/W See table 13.2.
7
C0MID5 0
R/W Transfer request module ID for DMA channel 0 (MID)
6
C0MID4 0
R/W See table 13.2.
5
C0MID3 0
R/W
4
C0MID2 0
R/W
3
C0MID1 0
R/W
2
C0MID0 0
R/W
1
C0RID1 0
R/W Transfer request register ID for DMA channel 0 (RID)
0
C0RID0 0
R/W See table 13.2.
Rev. 1.00 Dec. 27, 2005 Page 471 of 932
REJ09B0269-0100