SH7712 Datasheet, PDF (307/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Figure 9.1 shows a block diagram of the UBC.
Access
ASID Control
XAB/YAB
IAB LAB
Access
comparator
Address
comparator
ASID
comparator
Channel A
Section 9 User Break Controller
BBRA
BARA
BAMRA
BASRA
MDB
Access
comparator
Address
comparator
ASID
comparator
Data
comparator
Channel B
PC trace
CONTROL
BBRB
BARB
BAMRB
BASRB
BDRB
BDMRB
BETR
BRSR
BRDR
BRCR
LDB/IDB/
XDB/YDB
CPU state
signals
[Legend]
BBRA:
BARA:
BAMRA:
BASRA:
BBRB:
BARB:
BAMRB:
Break bus cycle register A
Break address register A
Break address mask register A
Break ASID register A
Break bus cycle register B
Break address register B
Break address mask register B
User break request
UBC Location
CCN Location
BASRB:
BDRB:
BDMRB:
BETR:
BRSR:
BRDR:
BRCR:
Break ASID register B
Break data register B
Break data mask register B
Execution times break register
Branch source register
Branch destination register
Break control register
Figure 9.1 Block Diagram of User Break Controller
Rev. 1.00 Dec. 27, 2005 Page 265 of 932
REJ09B0269-0100