SH7712 Datasheet, PDF (33/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Figure 18.7 (2) MII Frame Transmit Timing (Collision)............................................................ 717
Figure 18.7 (3) MII Frame Transmit Timing (Transmit Error)................................................... 718
Figure 18.7 (4) MII Frame Receive Timing (Normal Reception)............................................... 718
Figure 18.7 (5) MII Frame Receive Timing (Reception Error (1))............................................. 718
Figure 18.7 (6) MII Fame Receive Timing (Reception Error (2)) .............................................. 718
Figure 18.8 MII Management Frame Format ............................................................................. 719
Figure 18.9 (1) 1-Bit Data Write Flowchart ............................................................................... 720
Figure 18.9 (2) Bus Release Flowchart (TA in Read in Figure 18.8) ......................................... 721
Figure 18.9 (3) 1-Bit Data Read Flowchart ................................................................................ 721
Figure 18.9 (4) Independent Bus Release Flowchart (IDLE in Write in Figure 18.8)................ 722
Figure 18.10 Changing IPG and Transmission Efficiency ......................................................... 723
Figure 18.11 Diagram of Qtag Additional Functions ................................................................. 724
Figure 18.12 Comparison of Normal Ethernet Frame and IEEE802.1Q Frame (with Qtag)...... 724
Figure 18.13 Example of Connection to DP83847 ..................................................................... 725
Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
Figure 19.1 Configuration of E-DMAC, and Descriptors and Buffers....................................... 728
Figure 19.2 Relationship between Transmit Descriptor and Transmit Buffer ............................ 755
Figure 19.3 Relationship between Receive Descriptor and Receive Buffer ............................... 761
Figure 19.4 Sample Transmission Flowchart (Single-Frame/Two-Descriptor) ................................ 768
Figure 19.5 Sample Reception Flowchart (Single-Frame/Two-Descriptor) ............................... 770
Figure 19.6 E-DMAC Operation after Transmit Error ............................................................... 771
Figure 19.7 E-DMAC Operation after Receive Error................................................................. 772
Figure 19.8 Configuration of ARBUSY ..................................................................................... 773
Figure 19.9 Summary of Receive FIFO Overflow Alert Signal ................................................. 774
Figure 19.10 ARBUSY Signal Change and Minimum Pulse Width Depending on
Increase and Decrease of FIFO ............................................................................. 775
Section 22 User Debugging Interface (H-UDI)
Figure 22.1 Block Diagram of H-UDI........................................................................................ 791
Figure 22.2 TAP Controller State Transitions ............................................................................ 802
Figure 22.3 H-UDI Data Transfer Timing.................................................................................. 804
Figure 22.4 H-UDI Reset............................................................................................................ 804
Section 24 Electrical Characteristics
Figure 24.1 Power On/Off Sequence .......................................................................................... 856
Figure 24.2 EXTAL Clock Input Timing ................................................................................... 861
Figure 24.3 CKIO Clock Input Timing....................................................................................... 861
Figure 24.4 CKIO Clock Output Timing.................................................................................... 862
Figure 24.5 Power-On Oscillation Settling Time ....................................................................... 862
Figure 24.6 Oscillation Settling Time at Standby Return (Return by Reset).............................. 862
Figure 24.7 Oscillation Settling Time at Standby Return (Return by NMI)............................... 863
Rev. 1.00 Dec. 27, 2005 Page xxxiii of xlii