SH7712 Datasheet, PDF (645/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 17 Serial I/O with FIFO (SIOF)
17.3.8 SIOF Status Register (SISTR)
SISTR shows the SIOF state. Each of the bits of this register becomes an SIOF interrupt source
when the corresponding bit in SIIER is set to 1. SISTR is initialized by a power-on reset or
software reset.
Initial
Bit Bit Name Value R/W Description
15 —
0
R Reserved
This bit is always read as 0. The write value should always be
0.
14 TCRDY 0
R Transmit Control Data Ready
This bit indicates a state of the SIOF. If SITCR is written, the
SIOF clears this bit. This bit is valid when the TXE bit in SICTR
is set to 1. If the issue of interrupts by this bit is enabled, the
SIOF issues a control interrupt. If SITCR is written when this
bit is cleared to 0, SITCR is over-written and the previous
contents of SITCR are not output from the TXD_SIO pin.
0: Indicates that a write to SITCR is disabled
1: Indicates that a write to SITCR is enabled
Note: When using this bit, see 2 in section 17.5, Usage Notes.
13 TFEMP 0
R Transmit FIFO Empty
This bit indicates a state; if SITDR is written, the SIOF clears
this bit. This bit is valid when the TXE bit in SICTR is 1. If the
issue of interrupts by this bit is enabled, the SIOF issues a
control interrupt.
0: Indicates that transmit FIFO is not empty
1: Indicates that transmit FIFO is empty
12 TDREQ 0
R Transmit Data Transfer Request
A transmit data transfer request is issued when the empty
space in the transmit FIFO exceeds the size specified by the
TFWM bit in SIFCTR. This bit is valid when the TXE bit in
SICTR is 1. This bit indicates a state of the SIOF. If the size of
empty space in the transmit FIFO is less than the size
specified by the TFWM bit in SIFCTR, the SIOF clears this bit.
If the issue of interrupts by this bit is enabled, the SIOF issues
a transmit interrupt.
0: No transfer request
1: Transfer request
Rev. 1.00 Dec. 27, 2005 Page 603 of 932
REJ09B0269-0100