SH7712 Datasheet, PDF (815/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 19 Ethernet Controller Direct Memory Access Controller (E-DMAC)
19.3.5 Receive FIFO Overflow Alert Signal (ARBUSY)
The E-DMAC outputs the receive FIFO overflow alert signal (ARBUSY) to the EtherC to support
flow control function conforming to IEEE802.3x of the EtherC. The ARBUSY signal
synchronized with the bus clock (B clock) signal is also output to an external pin of this LSI.
When the capacity of data received in receive FIFO or the number of receive frames reach the
threshold (RFF2 to RFF0, or RFD2 to RFD0) specified in FCFTR in E-DMAC, ARBUSY is
valid.
The threshold is the value less than the overflow value: 2048 − 64, 1792 − 32, 1536 − 32,
and 256 − 32 bytes.
Figure 19.9 shows the configuration of the receive FIFO overflow alert signal (ARBUSY) output.
As shown in figure 19.9, because the ARBUSY signal passes through the system clock
synchronization circuit, it is behind the receive FIFO overflow alert signal received in EtherC.
This LSI
E-DMAC0
Receive FIFO overflow
alert signal
E-DMAC1
Receive FIFO overflow
alert signal
EtherC
System clock
synchronization
circuit
ARBUSY
Figure 19.8 Configuration of ARBUSY
Rev. 1.00 Dec. 27, 2005 Page 773 of 932
REJ09B0269-0100