SH7712 Datasheet, PDF (829/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 21 I/O Ports
Section 21 I/O Ports
21.1 Overview
This LSI has three 8-bit ports (ports A to C). All port pins are multiplexed with other pin functions
(the pin function controller (PFC) handles the selection of pin functions and pull-up MOS control).
Each port has a data register which stores data for the pins.
21.2 Register Descriptions
21.2.1 Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores data for pins PTA7 to PTA0. Bits PA7DT
to PA0DT correspond to pins PTA7 to PTA0. PADR is initialized to H′00 by a power-on reset but
is not initialized by a manual reset, in standby mode, or sleep mode.
Initial
Bit Bit Name Value
7
PA7DT
0
6
PA6DT
0
5
PA5DT
0
4
PA4DT
0
3
PA3DT
0
2
PA2DT
0
1
PA1DT
0
0
PA0DT
0
R/W Description
R/W When the pin function is general output port, if the port
R/W
is read, the value of the corresponding PADR bit is
returned directly. When the function is general input
R/W
port, if the port is read, the corresponding pin level is
R/W
read. Table 21.1 shows the function of PADR.
R/W
R/W
R/W
R/W
Rev. 1.00 Dec. 27, 2005 Page 787 of 932
REJ09B0269-0100