SH7712 Datasheet, PDF (538/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 14 Timer Unit (TMU)
Pφ
Prescaler
Bus interface
Clock
controller
Ch. 0
Counter
controller
TSTR
TCR0
TCNT0
TUNI0
Interrupt
controller
Ch. 1
Counter
controller
TCOR0
TCR1
TCNT1
TUNI1
Interrupt
controller
Ch. 2
Counter
controller
TCOR1
TCR2
TCNT2
TUNI2
Legend
TSTR: Timer start register
TCR: Timer control register
Interrupt
controller
TCOR2
TMU
TCNT: 32-bit timer counter
TCOR: 32-bit timer constant register
Figure 14.1 TMU Block Diagram
Rev. 1.00 Dec. 27, 2005 Page 496 of 932
REJ09B0269-0100