SH7712 Datasheet, PDF (198/978 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series

Section 4 Exception Handling
Figure 4.1 shows the bit configuration of each register.
31
0
10 9
21 0
TRA
0
TRA
31
0
12 11
EXPEVT
0
EXPEVT
31
0
12 11
INTEVT
0
INTEVT
31
0
12 11
INTEVT2
0
INTEVT2
31
TEA
0
TEA
Figure 4.1 Register Bit Configuration
4.1.1 TRAPA Exception Register (TRA)
TRA is assigned to address H′FFFFFFD0 and consists of the 8-bit immediate data (imm) of the
TRAPA instruction. TRA is automatically specified by the hardware when the TRAPA instruction
is executed. Only bits 9 to 2 of the TRA can be re-written using the software.
Bit
Bit Name
31 to 10 
9 to 2
1, 0
TRA

Initial Value R/W

R

R/W

R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
8-bit Immediate Data
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 1.00 Dec. 27, 2005 Page 156 of 932
REJ09B0269-0100